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Allegro

Cadence (Allegro)

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Product Description

IC Packaging and Co-Design

pb_lg_ICPackaging

Allegro Package Designer

Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die or side by side die designs.

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Allegro Package SI

Delivers a virtual prototyping design and simulation environment for IC packages using accurate 3D simulation models. Direct read/write from the design database provides fast, accurate models for critical design decisions.

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Cadence 3D Design Viewer

Provides 3D visualization and wirebond design rule checking (DRC) for IC packages. Enables collaborative markups in a solid model viewer to modify wirebond profiles.

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Cadence OrbitIO

A system planning and prototyping solution that brings the multiple fabrics of silicon, interposer, package, and PCB together into a single-canvas co-design environment. It enables optimal device placement and connectivity assignment in context of the full system to produce well-qualified design definitions ready for expedited implementation.

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Cadence RF SiP Methodology Kit

Teaches proven RF SiP design techniques with examples from concept to manufacturing. Provides a complete software solution set for RF/wireless applications. Accelerates learning and productivity.

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Cadence SiP Co-Design

Flexible chip-package co-design methodologies with supporting utilities allow for customizable co-design flows that meet the organizational challenges associated with collaboration between chip and package design teams that may be globally distributed.

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