IC Packaging and Co-Design
Allegro Package Designer
Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die or side by side die designs.
Allegro Package SI
Delivers a virtual prototyping design and simulation environment for IC packages using accurate 3D simulation models. Direct read/write from the design database provides fast, accurate models for critical design decisions.
Cadence 3D Design Viewer
Provides 3D visualization and wirebond design rule checking (DRC) for IC packages. Enables collaborative markups in a solid model viewer to modify wirebond profiles.
A system planning and prototyping solution that brings the multiple fabrics of silicon, interposer, package, and PCB together into a single-canvas co-design environment. It enables optimal device placement and connectivity assignment in context of the full system to produce well-qualified design definitions ready for expedited implementation.
Cadence RF SiP Methodology Kit
Teaches proven RF SiP design techniques with examples from concept to manufacturing. Provides a complete software solution set for RF/wireless applications. Accelerates learning and productivity.
Cadence SiP Co-Design
Flexible chip-package co-design methodologies with supporting utilities allow for customizable co-design flows that meet the organizational challenges associated with collaboration between chip and package design teams that may be globally distributed.